Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems

A fundamental objective in the design of a network-on-chip is to minimize its area and power consumption while keeping the performance requirements at acceptable levels. The trade-offs involved in the process depend on the target technology, ASIC or FPGA. This paper presents a novel design approach to customize the routers in a network-on-chip for reconfigurable systems. More specifically, given a topology and the traffic requirements, the design process automatically finds the architecture of each router, adjusting the size of the buffers and the configuration of the switch matrix, such that the overall area and performance are maximized. The results indicate that the proposed algorithm can provide significantly better solutions compared to the uniform router design, which is typically used.