Better leakage reduction by exploiting the built-in MOSFET-Vth characteristics

Leakage has become one of the most dominant factors of power management and signal integrity of nanometer scale integrated circuits. Recently, power gating structures has proven to be effective in controlling leakage. In this paper an alternative dual-Vth reduced power gating structure is proposed for better reduction of leakage currents, especially for low-power, high-performance portable devices. The proposed technique maintains an intermediate power saving state as well as the conventional power cut-off state. Experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF power saving modes. It has also been demonstrated that the proposed technique significantly reduces ground bounce due to power mode transition.