SiGe cantilever channel gate-all-around (GAA) fully depleted (FD) PMOSFET with high-κ and metal gate

Scaling the conventional CMOS transistor beyond the 45 nm generation ushers in several fundamental limitations. Control of leakage currents and sustaining electrostatic integrity while maintaining historic enhancements in performance requires such ultra-thin gate-dielectrics and heavily doped bodies that a process window sufficiently large for manufacturing might not be found. While conventional SiO
₂
might need to be replaced by high-kappa dielectric and metal gate, it might be necessary that the conventional planar MOSFET architecture be also substituted to address the electrostatics challenges. In addition high mobility materials need to be explored to garner the additional enhancement in performance. In this paper we demonstrate a PMOSFET device architecture that integrates such a high mobility material with high-kappa/metal gate in a 3D non-planar gate-all-around architecture (GAA).