A floating-gate transmission-line model technique for measuring source resistance in heterostructure field-effect transistors

A simple technique to measure the parasitic source and drain resistances in heterostructure field-effect transistors (HFETs) is presented. The technique makes use of the unavoidable gate leakage current of a typical HFET under bias. Floating-gate measurements with current flowing from the source to the drain are carried out in a set of devices with different gate lengths. Extrapolation to zero gate length unequivocally and simultaneously yields both the source and drain resistances. No special test-pattern structure is required. The technique is demonstrated in In/sub 0.52/Al/sub 0.48/As/n/sup +/-In/sub 0.53/Ga/sub 0.47/As metal-insulator doped semiconductor field-effect transistors.<
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