Portless SRAM—A High-Performance Alternative to the 6T Methodology

A novel memory cell, termed “portless” SRAM, is presented as a direct alternative to the standard 6T design. The new cell consists of only five transistors and does not make use of any pass-transistor ports. A complete theoretical and functional analysis is presented along with a design methodology for implementing the new memory cell. In addition, simulations are presented on the cell level and on the cache level exhibiting comparative improvements on the order of 19$\,\times$ and 6$\,\times$ in dynamic power and leakage power respectively. This is augmented by a 20% improvement in static noise margin for a comparable cell area. A test chip was fabricated, and measured results are presented demonstrating functionality of the new cell.