FPGA-based Digital Phase-Sensitive Demodulator for EIT System

Electrical impedance tomography (EIT) requires high precision voltage measurement to reconstruct image. In this paper a novel FPGA-based digital phase-sensitive demodulator designed for EIT system is put forward. Unlike the traditional analog multiplier demodulator of poor dynamic behavior and high noise, the digital demodulation is used to obtain both in-phase and quadrature components of the voltage signal with high SNR, high data precision and high demodulation speed. This paper first expounds the theory of digital phase-sensitive demodulator, then discusses the blocks and technique specification of the demodulator. Different parts are realized by VHDL. The demodulator is implemented and tested. Emulation is given by QUARTUS II and the phase error is 1.03deg. The result shows that the digital demodulator is suitable for the signal processing in EIT system and meets the requirement of digitized EIT system.