An Experimental Comparison of Clock Distribution Networks for Systems on Chip

In this paper, an evaluation of experimental results from clock distribution networks fabricated for large systems on chip is presented. Typical 3.3V 0.35μm CMOS N-well AMIS process parameters were used for the chip fabrication and analysis. It is shown that local networks represent an appropriate approach when used in system on a chip since these networks are comparable in performance to global nets but more robust under process variations.