A Novel DRAM Cell Transistor Featuring a Partially-insulated Bulk FinFET (Pi-FinFET) with a pad-Polysilicon Side Contacts (PSC)

The pad-Polysilicon Side Contact (PSC) has drastically improved the performance of the Partially-insulated bulk FinFET (Pi-FinFET). PSC enabled to dope a source and drain (S/D) of the fin structure uniformly from the top of the fin to the Pi layer. Since the uniform S/D increases effective channel width, the drivability was increased by 100% compared to the conventional bulk FinFET cell. Nevertheless, Hot Carrier (HC) lifetime was extended because the position of the highest electric field was nearer to the gate edge compared to the conventional. The total junction leakage current became 50% of the conventional due to the Pi layer. Undoped silicon Selective Epitaxial Growth (SEG) buffered PSC could control Gate Induced Drain Leakage (GIDL) to the same level of conventional bulk FinFET. In addition, by optimizing fin height, 25% less word line capacitance (C
WL
) was achieved. We place this Pi-FinFET with PSC is one of the promising candidates for the future FinFET DRAM cell technology.