Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme

Using strained SiGe on Si, the threshold voltage of high κ PMOS devices is reduced by as much as 300 mV. The 80 nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La
₂
O
₃
capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high κ and metal gates for 32nm node and beyond.