Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process Window

We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-V
_T
NMOS and PMOS devices with 725/370 mμ/μm (at V
_DD
=1.1 , I
_off
=20pA/μm and J
_g
= 100/1 mA/cm
²
). We demonstrate that adding embedded Si
_0.75
Ge
_0.25
in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the V
_T
distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni
₃₁
Si
₁₂
or Ni
₂
Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: -shifting up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; -extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.