Effectiveness of CMOS Charge Reflection Barriers in Space Radiation Environments

Single event upsets in microelectronic circuits follow the collection of more than some critical amount of charge at certain reverse-biased junctions. Reducing charge collection at the junctions lowers the upset rate without requiring performance tradeoff. Three mechanisms for reducing the fraction of charge collected at a junction can be incorporated in the use of CMOS-type wells. For illustration the CHMOS-III-D process used in Intel's P51C256 is shown to lower the error rate to be expected in deep space by an order of magnitude from that calculated for an equivalent dRAM of standard design.