Power-Aware Compiler Controllable Chip Multiprocessor

Chip multi-processors (CMP) have attracted much attention since they achieve higher performance not by raising operating frequency but by utilizing a number of transistors in parallel. However, simply increasing the number of processor elements (PE) will result in raising power consumption. This work presents a power-aware compiler controllable heterogeneous CMP and its performance and power evaluation with the OSCAR (optimally scheduled advanced multiprocessor) parallelizing compiler (K. Ishizaka et al., 2004).