High Speed Processor for FASTBUS

This paper describes a processor designed to operate at a speed compatible with fastbus. It has been used in an experiment at the AGS in Brookhaven National Laboratory. Its function was to read data from various fastbus modules and store it in a buffer where it could later be read and further processed by a slower host computer. The data was formatted so that the host computer could more easily process it. The processor also made decisions based on the validity of the data and rejected bad events. The ratio of the number of triggers to the number of accepted events was about 20 to 1.