Power and Ground Bounce Effects on Component Performance Based on Printed Circuit Board Edge Termination Methodologies

Printed circuit boards (PCBs) are one source of radiated EMI with digital components the culprits. To minimize development of common-mode currents within the silicon package of large current consuming circuits, a stable power distribution network (PDN) is required. Any noise (bounce) on either the power or 0 V reference (ground) plane may cause simultaneously switching noise (SSN) or signal integrity (SI) problems, as well as EMI. In addition, if planar bounce exceeds margin levels, components may not function. To ensure a stable PDN is present, decoupling capacitors and buried capacitive structures are mandatory, along with minimizing loop inductance. The uniqueness of this research lies in analyzing planar bounce that may exceed voltage margin levels from reflected EM waves that propagate back to components from the physical edge of the PCB. The edges of a PCB are in reality a high-impedance, non- terminated signal transmission line stub. With each reflection, ringing occurs. The magnitude of this ringing may cause digital components to have SSN and/or EMI problems. Popular board edge termination techniques are invested to determine if a designer should be concerned with reflected wave switching noise on either a power or 0 V reference plane, which cannot be removed by capacitive structures or decoupling.