A 5-bit Interpolating Flash ADC in 0.13-μm SiGe BiCMOS

In this paper, the interpolating comparator technique is shown to reduce the power dissipation of a flash ADC. We report on the design of a S-bit interpolating flash converter to validate our assertion. The ADC has been simulated in a 0.13-μm 2.5-V SiGe BiCMOS technology. The total static power dissipation is 66.14 mW. This is half the power dissipation incurred by a conventional full-flash converter of similar design. No apparent performance penalty was incurred. The linearity performance achieves a differential nonlinearity (DNL) of 0.114 LSB and an integral nonlinearity (INL) of 0.076 LSB at 2-GSample/s with an ENOB of 4.3 bits.