High Voltage LDMOS Transistors utilizing a Triple Well Architecture

We present the integration, device fabrication as well as a reliability analysis of 36 V drain extended CMOS transistors into a 0.35 CMOS baseline technology by utilizing the existing implants and adding 2 additional masking layers. Breakdown voltages >70 V for DENMOS and >60 V for DEPMOS are achieved employing the drain extended device structure. These high breakdown voltages can only be achieved because of careful junction design.