A 70V UMOS Technology with Trenched LOCOS Process to Reduce Cgs

A trenched LOCOS process has been applied to a UMOS structure to reduce the gate-to-source overlap capacitance (C
_gs
). A 40% reduction in C
_gs
is achieved comparing to conventional UMOS, and the device's specific on- resistance R
_on,sp
= 60mΩ·mm
²
is observed. The improvement in device figure-of-merit(FOM = R
_on
×Q
_g
) is about 58%.