An Alternative Logic Approach to Implement High-Speed Low-Power Full Adder Cells

This paper presents a high-speed low-power 1-bit full adder cell designed upon an alternative logic structure to derive the SUM and CARRY outputs. Hspice and Nanosim simulations show that this full adder cell designed using a 0.35μm CMOS technology and supplied with 3.3V, exhibits delay and power dissipation around 720ps and 840μW, respectively. These features reflect an overall improvement of 30% in the power-delay metric, when compared with the performance of other realizations recently published as well featured cells for low-power applications.