Technology Optimizations for Giaever Transformer Based on HTS Heterostructure

In this paper, we present several steps in the development of an HTS Giaever transformer, based on a SIS heterostructure, where both superconducting thin film should present low pinning properties and be insulated with a thin insulating layer. High Resolution AC Susceptibility measurements on YBCO//STO and NBCO//STO thin films show that the most important pinning centers are twin boundary intersections (TBI), and that their elimination with proper growth conditions allows to improve vortex mobility. When the base layer outgrowth density exceeds 10
⁵
/cm
²
, pinholes through the insulating layer (PBCO/STO) short-circuit the electrodes. Therefore, ion beam milling at grazing incidence has been performed to reduce the height of the outgrowths otherwise protruding between 0.5 and 1.5 mum above the surface of the film. We could reduce their density by 10 and barrier leakage by 1000 with only 10 nm of insulator thickness. Several Giaever devices were fabricated with this ion milling process and by adjusting the regrowth temperature. The influence of this new technology was investigated: AES analysis indicates a preferential erosion of copper ions, a damaged surface layer of 5 nm is deduced from RBS analysis.