A Comparison Between Noise-Immunity Design Techniques for Dynamic Logic Gates

In this work, we analyze three design techniques to enhance the noise immunity of dynamic logic gates. A comparison in Power Consumption, Average Noise Threshold Energy (
ANTE
) and
ANTE
- normalized energy (
EANTE
) between the three techniques is presented. The dynamic logic gates using noise immunity techniques were designed with 0.35
μ
m, 0.18
μ
m, and 0.09
μ
m CMOS process technologies and power supply of 3.3V, 1.8V, and 1.0V respectively. The obtained results show that for all technologies used in the simulations the Transparency Window technique [1] presents the best trade-off among noise immunity and performance as technology scales.