A High Speed Flexible Encoder for Low-Density Parity-Check Codes

Encoder implementations of low-density parity- check codes are typically optimized for area due to their high complexity. Such designs usually have relatively low data throughput. Two new encoder designs are presented here that achieve much higher data rates while requiring more area for the implementation. One of these design achieves encoding rates in excess of 400 Mbps. All of the designs presented can fit on FPGAs currently available. The methodology for both designs and performance results are presented.