Noise Suppression in a Class-D Amplifier Using a Three-Level Converter

An architecture that reduces the harmonics of the output signal of a class-D amplifier using a three-level converter has been proposed. The structure consists of a sigma-delta modulator which converts a 15-bit input signal into a 2-bit signal at the clock frequency of 2.822 MHz. This signal drives a three-level diode clamped output power stage. The proposed structure, designed and simulated using 2.5V TSMC 0.25u process, enables the in-band noise suppression, improves the signal-to-noise ratio and reduces the switching losses and hence the complexity of the low-pass filter at the output.