An Optimized Pipelined-Subranging ADC Architecture

This paper reports an optimized pipelined-subranging ADC architecture that features new design techniques, such as, multiple MDACs, multiple open-loop residue amplifiers, relative comparison method and closed-loop circular resistive interpolation network. Multiple MDACs and multiple residue amplifier relaxes the linearity requirement down to the level that can be readily handled by the open-loop structure for fast settling while maintaining low power consumption. Relative comparison method helps to suppress the gain error caused by the inaccurate open-loop gain. The trade-off between speed and accuracy is broken by the circular resistive interpolation network. The new ADC architecture is successfully verified in design of a 12bit 100Msps pipelined-subranging ADC in commercial 0.35μm CMOS technology with the following specifications achieved: 2Vpp differential input range, ±0.6LSB DNL, 70dB SFDR, 62dB SNDR, ± 2% FS gain error, power dissipation of 520mW and a die size of 9mm2