High-Speed Hybrid Parallel-Prefix Carry-Select Adder Using Ling's Algorithm

Parallel-prefix adders offer high efficiency solution in terms of area, speed, power and regularity to the binary addition problem and are well suited for VLSI implementation. In this paper, a novel technique of implementing a hybrid parallel- prefix ling adder is presented. Experimental results show that the proposed adder has an improvement of 63% in speed and about 13% reduction in power consumption compared to Carry Lookahead adder (CLA).