Implementation and Synthesis of a Sorting Network

In this paper, we represent sorting algorithm and operation procedure of a sorting network that is a "parallel sorter". This sorter has been programmed by "active-HDL" software and has been examined by "FPGA express" software for being able to be synthesized on FPGA chips. Due to using a structure almost like pipelining, input data and output data are independent of each other, so it is possible to load new unsorted data from input port and to transmit sorted data to output port at the same time. One main attributes of this sorting network program is that it can be easily modified for sorting favorite unsorted data numbers and desirable data length. In this sorter, "N" unsorted data are sorted (from largest to smallest) in maximally "N+2" clock cycles.