Test Circuit for Study of CMOS Process Variation by Measurement of Analog Characteristics

We propose and demonstrate a test chip for extraction of spatial and layout dependent variations in both transistor and interconnect structures. A scan chain approach is combined with low-leakage and low-variation switches, providing access to detailed analog device characteristics in large arrays of test devices. Compared to digital test structures such as ring oscillators, the test circuit enables flexible extraction and analysis of variation in any device model parameters based on current-voltage measurements.