Circuit Simulation of Threshold-Voltage Degradation in a-Si:H TFTs Fabricated at 175 $^{\circ}\hbox{C}$

This brief presents a novel approach to modeling gate bias-induced threshold-voltage (V
_th
) degradation in hydrogenated amorphous silicon thin-film transistors (TFTs). The V
_th
degradation model is added to the SPICE 3.0 TFT device model to obtain a composite model and is verified by comparing the simulated V
_th
shift with measured data in a TFT latch circuit.