Competitiveness and Technical Challenges of Low Cost Wirebond Packaging for High Speed SerDes Applications in ASICs

This paper discusses the challenges in balancing the wireability, performance, and cost of low cost wirebond packaging for high speed SerDes applications in application specific integrated circuits (ASICs). In-depth analysis was performed using 3D electromagnetic simulation to evaluate the effect on performance of various design factors along the signal path of the wirebond package, including bondwire, microstrip, and ball grid array (BGA) assignment. The tradeoff between wireability and performance of these design factors is discussed. Hardware measurements were performed on a functioning high speed SerDes test site which was designed to optimize wireability for the application while still achieving performance well beyond the 3 gigabits per second (Gbps) data rate for which it was designed. Projections are made concerning design variables that can be adjusted to meet the requirements of wire count, package size, and performance, enabling the ability to design for a broad application space in high speed SerDes applications.