Sloped Through Wafer Vias for 3D Wafer Level Packaging

Through silicon via (TSV) technology is one of the critical and enabling technologies for 3D chip stacking. Many TSV approaches that have been demonstrated are application specific; and there is a great need for generic solutions. This work describes the design, fabrication and characterization of a TSV technology for silicon substrates where the interconnects are fabricated typically after standard CMOS processing and can be applied to any silicon based technology. This so-called 3D Wafer Level Packaging (3D-WLP) technology die stacking is based on a the thinning first, via last approach: the via is fabricated from the backside of a thinned wafer. Plasma etching of the wafer is used to achieve sloped profile which allows the conformal deposition of the dielectric layer and copper seed metallization. The vias are isolated from the substrate using polymer dielectrics; and spray coating of photoresist is used to pattern the dielectric within the vias. Electrical connection between the front and the back of the wafer is achieved by partial filling of the vias with copper. All processes employed in the fabrication of sloped through wafer vias are performed using standard wafer handling and at low temperature (< 250°C) for post CMOS compatibility. Various dimensions of TSVs are fabricated and electrically characterized by four point measurements. The measurements and calculations on daisy chains connecting a number vias in series show that the via resistance is in the range of 20-30mΩ depending on the via size. We believe that this generic 3D-WLP via approach is suitable for many 3D applications.