Chip Embedded Wafer Level Packaging Technology for Stacked RF-SiP Application

In this paper, chip to wafer stacking and embedding active components by wafer level technologies were described. The radio frequency (RF) module-like component was chosen as the test vehicle in this study. Analog wafer were treated to less than 50μm thickness and then singulated. The thin chip were die bonded, by chip stacking method, on to the digital wafer and embedded by lamination of dielectric layers, Aginomoto build up film (ABF) in this case. Laser drilling process was adapted to open the via to the pads on the analog chips and digital wafers. The vias and traces were Cu plated to form the interconnection between the chips and the component IO pads. Results of this study show the benefits of the structure can provide more precise alignment and more reliable chip to wafer stacking without any voids or defects. Meanwhile, the presented wafer level process gives a much simple and cost effective package. Besides, high aspect ratio build up process by multi-layer ABF lamination and Cu interconnection were well developed. By the described process integration, vertical chip stacked and embedded RF module within 300μm thickness, excluding the solder ball, could be demonstrated. All the realization of this small size RF module will be revealed in more detail. Reliability tests such as the 288°C solder dipping and 260°C level 3 preconditioning test were carried out to further clarify the component property. Results of the reliability test and the corresponding failure analysis were described in this paper.