A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing

A low-voltage design is developed for amplifiers in the pipelined ADC, regulating overdrive voltage to be constant over PVT variations. A prototype 10b 80MS/S pipelined ADC is fabricated in a 90nm CMOS process. The ADC consumes 6.5mW from a 0.8V supply and occupies 1.18 times 0.54mm
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