A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer

Fabricated in 90nm CMOS, the chip consumes 545mW and has a pattern-balancing adaptive equalizer that is stable for any data patterns including those with a strong peak component at a single frequency. The adaptive equalizer yields a gain at f
_s
/2 relative to f
_s
/16 varying from -1.7 to 2.2dB for any 8B10B encoded Ethernet frames filled with a fixed data byte