A One-Cycle Lock Time Slew-Rate-Controlled Output Driver

A low-power output-on-demand slew-rate-controlled output driver is presented. It has an open-loop digital scheme and a one-cycle lock time applicable to high-speed memory interfaces. The output driver maintains slew rate between 2.1V/ns and 3.6V/ns for the SSTL interface. Fabricated in a 0.18mum CMOS process, the control block of the proposed driver occupies 0.009mm
²
and consumes 13.7mW at 1Gb/s. No external resistance is needed to calibrate the output resistance of the output driver.