A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS

A quarter-rate CDR circuit is based on a dual-loop approach where sampling phases are generated by a phase-programmable PLL that is controlled by a digital DLL. Implemented in 65nm SOI CMOS, the chip occupies 0.03mm
²
and consumes 1.8mW/Gb/s. Measurements confirm 40Gb/s operation with a BER <10
^-12
at a maximum frequency-offset of 400ppm. The phase relation between data and edge samples can be programmed within plusmn0.1 UI.