LVSMOS: an I/O-Cell-Friendly ESD and Latchup Robust Structure for CMOS Submicron Technologies with Compact Cell Design

The ESD performance of standard CMOS I/O cells can be significantly enhanced by placing a shorted p-n diode adjacent to the NMOS connecting to the pad. The NMOS ESD is enhanced through vpnp holes injection into substrate and activation of an embedded SCR. Typically, It2 doubles with Vhold above VDD.