Dynamically Reconfigurable Adaptable MultiModule Based Synthesis of DSP Data Flow Graphs

Most of architectural synthesis techniques target DSP algorithms onto multiprocessor architectures using basic functional units such as adders or multipliers. In this paper, a scheme for the partitioning of the data flow graph of a DSP application for a high-level synthesis aimed at a design using multi-modules is proposed. In the propose scheme, the regularity characteristics of DSP application are exploited. Moreover, in order to reduce the number of distinct modules, the near-isomorphism sub-graphs represents the modules are merged together by multiplexing them in time to produce a single adaptable module. This merging process enables the reuse of the adaptable modules by partially reconfiguring them at run time to realize different modules during the running of the DSP data flow graph. It is seen that a small overhead in terms of the architecture's controller is needed by the modules in order for them to be adapted to perform different computations (multi-modes).