Extraction of Primitives from ZF-SQRD Algorithm for a DSP Platform

Implementing complex algorithms on hardware platforms is time consuming. In order to reduce the software efforts needed to implement new algorithms on either a single or multiple digital signal processor platform, it becomes very relevant to predict various metrics. The number of cycles required for an Arithmetical/Logical Unit (ALU) to process an algorithm, memory usage, both ratios data/MIPS and MlPS/data, power consumption are good metrics' illustrators. This paper is focused on the prediction of the resources required by the ALU of a TMS320C6711 processor (Texas Instruments) in order to process in real-time, data through zero forcing sorted QR decomposition (ZF-SQRD) algorithm. A brief description of the ZF-SQRD algorithm and the methodology used to perform the predictions are presented. Moreover, the results of the studies show that for different number of antennas at the transmitter and at the receiver, the expected number of cycles values are quite similar to the simulation ones under appropriate simulation settings.