Structured Logic Arrays for Future CMOS Technologies

As we continue to scale the dimensions of transistors and wires in the deep submicron (DSM) era, the resolution of photolithographic processes is quickly reaching its limits and causing problems in the reliable manufacture of integrated circuits. The design methods using standard cell ASICs (SC-ASIC) produce randomly placed gates and interconnects which are difficult to fabricate at fine geometries, such as 65 nm and below. Besides reduced yield, they also suffer from high testing cost, even with the most advanced built-in self-test methods. These shortfalls motivated us to search for more structured logic architectures for future technologies that can be fabricated more easily and are better suited to self-test, and eventually self-repair. In this paper, we focus on programmable logic arrays to explore their potential when competing for speed, area and power with SC-ASIC. We will investigate the critical path delay for clock-delayed PLAs and provide equations for quick estimation of capacitive loads, delays and areas using technology-independent parameters. These equations can be used in front-end CAD tools for partitioning and architecture decision-making before the logic is implemented in a specific technology. We analyse the PLA to determine optimal sizes for logic implementation. We find that circuits with higher than 200 product terms have slower PLA implementations than SC-ASIC. They often take more than 10 times the area of SC-ASIC designs. To overcome these problems, we introduce methods to subdivide the slower PLAs in order to improve the overall circuit timing and area. For example, by dividing a circuit into two PLAs, we can cut its delay by half and keep the increase in area minimal.