Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics

The paper presents the results of simulations of voltage-induced V
_ccmin
drift of SRAMs fabricated with high-k gate dielectrics. The authors show that high-k based SRAMs are fundamentally more susceptible to V
_ccmin
stability problems because PMOS NBTI and NMOS PBTI lead to an additive degradation in the bit-cell read voltage. Given the differing time dependences of the NBTI and PBTI phenomena, the drift of V
_ccmin
is enhanced at much earlier times compared to SRAMs that have SiO
₂
gate dielectric only devices. Maintaining V
_ccmin
stability presents a significantly greater challenge for high-k gate dielectrics compared to SiO
₂