Mapping the Physical Layer of Radio Standards to Multiprocessor Architectures

We are concerned with the software implementation of baseband processing for the physical layer of radio standards ("software defined radio - SDR"). Given the constraints for mobile terminals with respect to power consumption, chip area and performance, nonstandard architectures without compiler support are the targets a SDR implementation has to face. For this domain we present a way to safely move from a functional model to the assembly level in order to come to a tested multithreaded optimized implementation in manageable time. We carried out this program for the standards WLAN IEEE 802.11b and 3GPP WCDMA exploiting various levels of parallelism: thread level parallelism ("MIMD"), data level parallelism ("SIMD") and instruction level parallelism ("VLIW"). We came up with a software implementation running in real time on Infineon's programmable multiple SIMD core (MuSIC) processor