A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost

Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn MLV controller, our technique can take this overhead into account. Ignoring this overhead during solution exploration may bring a side effect that is misrecognizing a non-optimum solution as an optimum one. Experimental results show that our algorithm can reduce the leakage current up to 48% and can find the optimum solutions on 22 out of 26 small MCNC benchmark circuits.