Minimum Phase Response in Digitally Controlled Boost and Flyback Converters

This paper addresses modeling and control issues related to practical high-frequency digital PWM control of constant-frequency boost, buck-boost and flyback converters. Discrete-time models, including the effects of A/D sampling and delays in the digital control loop, are derived for two cases: output voltage A/D sampling during transistor off time in combination with trailing-edge (TE) DPWM, and A/D sampling during transistor on time in combination with leading-edge (LE) DPWM. We show that off-time sampling with TE-DPWM, which is a common approach in digital controller realizations, can result in desirable minimum-phase responses, thus simplifying compensator design in wide bandwidth closed-loop voltage regulators based on boost or flyback converters. The results are verified by simulation and experimental results on a boost converter prototype.