A Novel Approach to Digitally Controlled Phase Locked Loop Tuning Systems

Digital Phase Locked Loops are commonplace today in voltage controlled oscillator applications. These PLL's are convenient to use since they are easily interfaced to a microprocessor which can be used to provide the intelligence for tuning control. They are also quite stable and well predictable with regard to frequency selection of the loop being controlled. However, there are a number of drawbacks which surface when such things as resolution and spurious response generation are evaluated. This paper will address a possible solution to some of these drawbacks. It describes a method by which the Reference (R) and the Select (N) divide chains may be manipulated concurrently in order to achieve much higher frequency resolution than normally thought possible while retaining a reasonable phase detector frequency. The frequency of the phase detector is a major contributor to spurious responses. These manifest themselves as sidebands above and below the normal VCO frequency at which the loop is locked. By using this variable N & R technique the phase detector frequency can in many cases be raised to a high enough frequency where it can be more easily filtered and thusly reduce the spurious response problem.