A Novel Wide-Range Delay Cell for DLLs

This paper describes a new architecture for delay cell that is used in the voltage-controlled delay line of analog delay locked loops. The proposed delay cell has differential configuration so it exhibits a good performance to supply and substrate noises. A wide operating range delay line is designed using this delay cell and in order to verify its operation, it is used in an analog DLL. The circuit design and ADS simulation are carried out by TSMC 0.18 mum CMOS process. Simulation results show that the frequency range of the delay line that use this delay cell is increased to 50% in comparison with previous architectures. Frequency range of the delay line is 120 to 420 MHz.