Optimization of Sub-Melt Laser Anneal: Performance and Reliability

A thermo-mechanical stress model (TMS) is presented to explain the impact of sub-melt laser anneal (LA) on SiON dielectric and on the overall transistor performance. An L
_gmin
reduction of 15nm/5nm for nMOS/pMOS over our poly-Si/SiON reference, with 8% capacitance and 10% source and drain resistance (R
_SD
) improvement, is demonstrated. Best device performance and NBTI immunity are reached by lowering the laser power and optimizing the nitrogen and fluorine profile. This minimizes the increase of Si dangling bonds at the SiON/Si interface and the oxide fixed charges, generated by the thermo-mechanical stress (TMS) during the LA fast thermal gradient. The full potential of LA is demonstrated by skipping the RTA. An Lgmin gain of 25nm/20nm is achieved for metal gate nMOS/FUSI gate pMOS devices over the junction RTA reference. Optimal 0.26 fF/mum overlap capacitance values (at V
_dd
= | 1 | V), 18%/ 23% for nMOS/pMOS lower CV/I product and pMOS improved R
_SD
are demonstrated