Low VT Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET Devices

We report band-edge pFET threshold voltage (V
_t
~ 0.28 V) for MoO
_x
N
_y
on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs V
_t
of 0.45 V using a MoO
_x
/SiON gate stack, meeting the requirement for 45nm high-V
_t
CMOS technology. 30 % improvement in performance compared to our base-line poly-Si/SiON was observed by using both MoO
_x
/SiON and MoO
_x
/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoO
_x
N
_y
gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices