Cycle-Accurate Performance Evaluation of Parallel Jpeg2000 on a Multiprocessor System-on-Chip Platform

Jepg2000 is a high-performance and flexible image compression algorithm whose practical integration within commercial products presently suffers from its labor-intensive and resource-demanding computational core. We investigated a multiprocessor implementation of Jpeg2000 encoder to demonstrate that a proper task allocation and communication architecture allows significant performance improvement. We devised a multiprocessor SoC architecture based on STMicroelectronics LX-ST230 VLIW processor nodes and set up an all-inclusive simulation environment to assess its overall performance. On average, we obtained a nearly Amdahl-optimal speedup with respect to the single processor solution, for color image compression