An All-Digital, High Data-Rate Parallel OQPSK Demodulator for Very Low SNR Signals

This paper describes a synchronization scheme and its parallel implementation structure suitable for an all-digital, high data-rate parallel OQPSK receiver with low discernible signals. Conventional synchronization scheme of OQPSK receiver with Costas phase recover loop followed by Gardner's timing recover loop can hardly converge when SNR is lower than 3 dB. The proposed synchronization scheme in this paper may operate with very low discernible signals with the value of E
_b
/N
₀
as low as -2 dB, with short acquisitive time. Moreover, the paper proposes a parallel demodulator architecture that based on block digital filter to make possible the FPGA implementation of the high data-rate demodulator, with date rate as high as several hundred megabits per second. Fixed-point simulation shows that the proposed demodulator only degrades about 0.2 dB SNR comparing with theoretical performance over AWGN channels without acquisition preambles