Parallel Genetic Algorithm for VLSI Building Block Layout

The VLSI building block layout (BBL) becomes a more and more important problem for VLSI physical design. In this paper, a multithread scheme for parallelizing a genetic algorithm for BBL placement optimization is presented. The parallel genetic algorithms (PGA) are realized, using sequence-pair (SP) as the representation. Parallel algorithm can be used either to speed up a problem or to achieve a higher accuracy of solutions to a problem. Our experimental results on a SUN workstation with 4 CPUs have shown that the scheme is effective in improving performance of placement over that of a sequential implementation