A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays

A test-structure comprising a dual-slope integrating analog-to-digital converter, auto-zeroing circuitry, digital control logic and a large array of devices under test (DUTs) has been developed to isolate threshold voltage variation. Threshold-voltage (V
_T
) isolation is achieved by testing all DUTs in the subthreshold regime where drain-to-source current is an exponential function of V
_T
. Spice simulations show that the structure is at least an order of magnitude more sensitive to V
_T
variation than to channel length variation. This, in combination with a hierarchical access scheme and leakage control system, allows efficient characterization of DeltaV
_T
for ~70,000 NMOS and ~70,000 PMOS devices in a dense 2mm times 2mm DUT array